| 摘要 |
<P>PROBLEM TO BE SOLVED: To realize a circuit size suited to applications without losing compatibility with existing resources. <P>SOLUTION: The bit length reducing unit 11 reduces the bit length of an operand expressed by a floating-point number and outputs the operand to a computing unit 15. The bit length increasing unit 12 increases the bit length of the computed result value represented by a floating-point number inputted from the computing unit 15, and restores the bit length to the original length. The bit length reducing unit 11 discards a preset number of higher-order bits of the exponent part of the floating-point number and at the same time adds a positive or negative offset value to the exponent part with the higher-order bits discarded, according to an application to be executed by the computing unit 15. The bit length increasing unit 12 restores the bits discarded by the bit length reducing unit 11 from the exponent part of the floating-point number and at the same time subtracts the offset value from the exponent part. <P>COPYRIGHT: (C)2013,JPO&INPIT |
