| 摘要 |
A memory interface circuit includes a clock signal supply buffer configured to send a system clock signal which is supplied through a reference node, to a memory through a transmission line; a data strobe buffer configured to receive a data strobe signal supplied from the memory; a system clock synchronizing circuit configured to supply a data read from the memory to a logic circuit in synchronization with the system clock signal; and a delay detecting circuit provided at a front stage to the system clock synchronizing circuit and configured to detect a transmission delay from the clock signal supply buffer to the data strobe buffer. The delay detecting circuit generates a phase difference data indicating the transmission delay based on a difference between a phase of the system clock signal and a phase of the data strobe signal outputted from the data strobe buffer, and supplies the phase difference data to the system clock synchronizing circuit. The system clock synchronizing circuit generates a read clock signal by shifting the system clock signal based on the phase difference data, and controls a supply timing at which the data is supplied to the logic circuit, based on the read clock signal. |
