| 摘要 |
A data synchronizer that receives an input stream of asynchronous digital data in packets, and provides an output stream of synchronous data in packets. The synchronizer includes a first memory unit and a second memory unit, each having a data input, a data output, a write clock input and a read clock input. A first switch is provided for switching connection of the input in alternating manner between the first memory unit input and the second memory unit input, and a second switch is provided for switching connection of the data synchronizer output in alternating manner between the first memory unit output and the second memory unit output. A write clock is provided to write clock inputs of the first and second memory units. The average data rate of the received valid data during the reception of the packet is determined, and a read clock is generated and provided to the first and second memory units at a rate corresponding to the average data rate of the received valid data bits during the reception of the packet being read. The switching of the first and second switches is controlled such that the switches switch between adjacent packets, with the second switch switching in opposite phase to that of the first switch. |
