| 摘要 |
A shaper of a periodic sequence of pulse packets with programmable pulse length, pause and quantity pulses in a packet comprises two reversible binary countdown counters, each of which having clock input, synchronous load enable input and data loading inputs, counter mode enable input, asynchronous reset input, overflow output, an inverter, OR element, a circuit comprising in series connected resistor and capacitor, a start-stop device comprising a synchronous D-type flip-flop having asynchronous reset, first and second two-input elements AND. Random RAM access memory built according register file circuit is incorporated, the bus forms independent write and read, which has data bus forming inputs to program the shaper for predetermined time parameters of pulses in a packet, write address bus, write enable input, read address bus, read enable input, asynchronous reset. |
