发明名称 DELAY CIRCUIT, DELAY CONTROLLER, MEMORY CONTROLLER, AND INFORMATION TERMINAL
摘要 <p>A delay circuit (131) according to the present invention is provided with a first delay unit (133) and a second delay unit (132) which are connected in series and generate a delay signal (153) by delaying an input signal. The first delay unit (133) has a first signal transmission path and changes a first delay quantity imparted to the input signal by switching, in accordance with a first delay control value (151), the signal transmission path on which the input signal is transmitted within in the first signal transmission path. The second delay unit (132) has a second transmission path and, in accordance with a second delay control value (152), changes a second delay quantity imparted to the input signal, without switching the second signal transmission path on which the input signal is transmitted.</p>
申请公布号 WO2012060066(A1) 申请公布日期 2012.05.10
申请号 WO2011JP05884 申请日期 2011.10.20
申请人 PANASONIC CORPORATION;MURAKAMI, DAISUKE 发明人 MURAKAMI, DAISUKE
分类号 H03K5/131;H03K5/14 主分类号 H03K5/131
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