PN JUNCTION GATED FIELD EFFECT TRANSISTOR HAVING BURIED LAYER

摘要

1,246,208. Semi-conductor devices. TEKTRONIX Inc. 13 May, 1969 [15 May, 1968], No. 24405/69. Heading H1K. In a JUGFET comprising a channel region located in a uniformly doped layer of the opposite conductivity type supported by a substrate of the same conductivity type as the channel, the part of the uniformly doped layer situated between the channel and the substrate constituting a gate region, a highly doped region of the same conductivity type as the uniformly doped layer is disposed between the gate and the substrate. The channel is provided with source and drain contacts and a gate contact is applied to the uniformly doped layer. Such a gate underlies the channel and may be termed a "bottom-gate". Under increasing reverse bias the depletion layer associated with the bottom gate-channel junction spreads out until it completely fills the uniformly-doped gate region. The provision of the highly doped layer allows the depletion layer to spread further so that the channel may be completely cut off. As shown, Fig. 1, Sb is diffused into part of the surface of a P type Si substrate 10 to form an N+ type region 14. An N type epitaxial layer 12 doped with P is grown on substrate 10, and B is diffused into an area of the epitaxial layer overlying the buried N+ type region 14 to form a P- type channel region 16. The portion 18 of the epitaxial layer 12 underlying the channel 16 constitutes the bottom-gate. B is diffused into the channel to form P type source and drain regions 22, 27, P is diffused-in to form N+ type top-gate region 26 and bottom-gate contact region 27, and B is diffused-in to form an isolating grid 30 surrounding the device and extending completely through the N type epitaxial layer 12. A1 source, drain and gate contacts 32 are applied to the top surface of the device. The exposed surface may be protected with an SiO 2 layer which may also be utilized as a diffusion mask using photoresist and etching techniques. The top-gate region 26 may be omitted. A plurality of FETs together with bipolar transistors may be produced in a single wafer to form an integrated circuit.