| 摘要 |
An ultra-low-cost three mask layers trench MOSFET and its method of manufacture, wherein the method includes posting a uniform-covering dielectric layer deposition, and then the topography of trenches with different open size is quite different, wherein the smaller open size trench is fully filled, while only bottom and sidewall are covered for the bigger one. After a patterned dry etch process, the bottom of the bigger trench is opened with dielectric spacer left on sidewall, and the smaller one is still filled with dielectric material. The remained dielectric material is used as masks for following N+ source implantation and/or P-body implantation. A self-aligned source contact process is performed using the remained dielectric material in the trench as hard mask, so the limitation coming from source contact trench to gate trench mis-alignment during photo process is eliminated. Therefore, the much higher cell density, means high device performance, could be achieved. |
