发明名称 |
Method to reduce a via area in a phase change memory cell |
摘要 |
A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer. |
申请公布号 |
US8101456(B2) |
申请公布日期 |
2012.01.24 |
申请号 |
US20080243759 |
申请日期 |
2008.10.01 |
申请人 |
BREITWISCH MATTHEW J.;JOSEPH ERIC A.;LAM CHUNG H.;SCHROTT ALEJANDRO G.;ZHU YU;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BREITWISCH MATTHEW J.;JOSEPH ERIC A.;LAM CHUNG H.;SCHROTT ALEJANDRO G.;ZHU YU |
分类号 |
H01L21/00 |
主分类号 |
H01L21/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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