| 摘要 |
Aspects of the disclosure provide a clock gate circuit for generating a clock signal. The clock gate circuit can include a multiplexer configured to receive a first logic signal at a first data input, a second logic signal at a second data input, and a reference clock signal at a selector input, and to output the clock signal having a logic state selected from one of the first logic signal or the second logic signal based on transitions of the reference clock signal. Further, the clock gate circuit can include a logic module coupled to the multiplexer and configured to output the first logic signal and the second logic signal based on an enable signal and the output of the multiplexer. |
