| 摘要 |
A duty cycle correction circuit comprises first and second pulse generators, a clock dividing unit, a detecting unit, and a pulse width control unit. The first pulse generator is configured to generate a first edge of a first pulse signal in synchronization with a first edge of a first clock signal, and the second pulse generator is configured to generate a first edge of a second pulse signal in synchronization with a second edge of the first pulse signal. The clock dividing unit is configured to generate a second clock signal by dividing the frequency of the first clock signal. The detecting unit is configured to generate a detecting signal according to the second clock signal and a time interval between the first edge of the first pulse signal and a second edge of the second pulse signal. In particular, pulse widths of the first and second pulse signals are the same and are adjustable according to a control signal from the pulse width control unit.
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