发明名称 Systems and methods for back end of line processing of semiconductor circuits
摘要 A BEOL manufacturing process for forming a via process between two metal lines on a semiconductor wafer comprises depositing a portion of a first metal adhesion layer within a patterned via hole, followed by a cooling step. The cooling step is then followed by formation of the remainder of the first metal adhesion layer and formation of a second metal adhesion layer within the patterned via hole. This process of forming the remaining portion of the first metal adhesion layer can be referred to as a wafer load, unload, load (LUL) process. By using a LUL process, thermal history is minimized, which reduces Al extrusion at the via interfaces.
申请公布号 US8003519(B2) 申请公布日期 2011.08.23
申请号 US20070847135 申请日期 2007.08.29
申请人 MACRONIX INTERNATIONAL CO., LTD. 发明人 LUOH TUUNG;HUANG CHI-TUNG;CHEN KUANG-CHAO;JIANG CANDY
分类号 H01L21/4763 主分类号 H01L21/4763
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