Shared memory multi video channel display apparatus and methods

摘要

The invention includes a system and the associated method for reducing memory access bandwidth in various sections of one or more video pipeline stages of one or more channels in order to produce multiple high quality video signals. Signal processing stages of a video processor may share portions of memory on and off chip to reduce memory access bandwidth. A blank time optimizer may receive a memory access request at a first clock rate and access the memory using a second clock rate which may be slower than the first to provide more bandwidth for another memory access request at the same or a later time. Video signals may be scaled relative to various memory access points to further reduce memory storage requirements. A color management unit may also be shared among one or more video signals by receiving combined video signals and identification information associated with each signal portion.