A METHOD AND APPARATUS TO PACK NEIGHBOR BLOCKS AND CELLS DURING THE AUTOMATIC CHIP LEVEL LAYOUT COMPACTION

摘要

PURPOSE: A block packing method and a standard cell packing method for automatic chip area optimization are provided to prevent wiring failure due to the congestion of hard blocks by securing an original area for wiring among the hard blocks and between the hard block and the standard cells. CONSTITUTION: An outline of all hard blocks is generated(S110). The outline is expanded with a merge factor(S120). The neighboring hard blocks which the outlines are overlapped each other are merged to one outline and make grouping(S130). The hard blocks within the group are merged to a small group in consideration of wiring between a standard cell and the hard blocks, and a bridge area is inserted between the small groups(S140). Hard block groups in which the bridge is inserted is packed to a group unit(S150).