发明名称 Phase lock loop and method for coded waveforms
摘要 A system and method is disclosed for maintaining synchronization in a communication system in which a signal is sent from a transmitter to a receiver which includes a phase lock loop. The receiver compares the output of a Viterbi decoder with the output of a quick decision circuit. The Viterbi decoder, which incorporates traceback, determines the minimum aggregate Euclidean distance for multiple symbols. The quick decision circuit determines the minimum Euclidean distance for a single symbol without decoding the symbol. If the difference in the output signals of the Viterbi decoder and the quick decision circuit is greater than a predetermined threshold, the phase error signal in the phase lock loop is prevented from updating the phase lock loop filter. A synchronization loss detector may also be used to prevent the phase error signal from updating the phase lock loop filter if synchronization loss is detected.
申请公布号 US7949082(B2) 申请公布日期 2011.05.24
申请号 US20070651566 申请日期 2007.01.10
申请人 HARRIS CORPORATION 发明人 HESSEL CLIFFORD;VOGLEWEDE PAUL E.
分类号 H03D3/24;H04L27/00 主分类号 H03D3/24
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