发明名称 |
Burn-in test circuit, burn-in test method, burn-in test apparatus, and a burn-in test pattern generation program product |
摘要 |
A burn-in test circuit according to the present invention includes a scan chain formed by a plurality of scan flip-flips connected in series, a circuit under test input with an output from one of the plurality of scan flip-flops as an activation signal, and a scan chain loop circuit being configured to an output signal of the scan chain determined according to an output of the circuit under test back to the scan chain.
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申请公布号 |
US7873887(B2) |
申请公布日期 |
2011.01.18 |
申请号 |
US20070619954 |
申请日期 |
2007.01.04 |
申请人 |
RENESAS ELECTRONICS CORPORATION |
发明人 |
HARADA EIJI |
分类号 |
G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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