发明名称 Wafer level chip scale package and fabricating method of the same
摘要 <p>PURPOSE: A wafer level chip scale package and a fabricating method of the same are provided to minimize stress on a solder ball by protecting a redistribution layer by using a non-oxidation metal layer. CONSTITUTION: A bonding pad is formed on a semiconductor chip(101). A first insulating layer(103) exposes a bonding pad from the semiconductor chip. A redistribution layer(104) is expanded from the bonding pad to the first insulating layer. A non-oxidation metal layer(105) is formed on the redistribution layer in order to cover up the redistribution layer. The non-oxidation metal layer has an auxiliary adhesion layer on one side thereof. A second insulating layer is formed on the first insulating layer. The second insulating layer exposes the non-oxidation metal layer. A solder ball(111) is formed on the auxiliary adhesion layer. The solder resist layer(110) is formed around the solder ball on the non-oxidation metal layer and the second insulating layer.</p>
申请公布号 KR101009158(B1) 申请公布日期 2011.01.18
申请号 KR20080064442 申请日期 2008.07.03
申请人 发明人
分类号 H01L23/48 主分类号 H01L23/48
代理机构 代理人
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