发明名称 DELAY FAULT TESTING COMPUTER PRODUCT, APPARATUS, AND METHOD
摘要 A computer-readable medium stores therein a program that causes a computer to execute acquiring for each chip, first delay values of paths in chips manufactured using circuit information concerning a circuit-under-test; building a function model representing a delay value of a path, based on the first delay values for the path and the circuit information; calculating a second delay value of a path included in and having the same configuration in each chip, using a built function model and the circuit information; comparing for each chip, a given calculated second delay value and the first delay value of a given path having a configuration identical to that of the path for which the given second delay value has been calculated; determining based on a comparison result, the given path to be a path that includes a delay error occurring irregularly according to chip; and outputting a determination result.
申请公布号 US2010299096(A1) 申请公布日期 2010.11.25
申请号 US20100778329 申请日期 2010.05.12
申请人 FUJITSU LIMITED 发明人 ISHIDA TSUTOMU
分类号 G06F19/00;G01R31/00;G01R31/28;G01R31/319 主分类号 G06F19/00
代理机构 代理人
主权项
地址