| 摘要 |
Disclosed is a semiconductor integrated circuit device operated in stability by high-speed clock signals and which is high in a cell using rate and in interconnection efficiency. In a mid part of a chip, there are provided an I/O 11b, supplied with a clock signal from outside, and a PLL 12, connected to the I/O 11b, and adapted for routing an internal clock signal, generated on the basis of the clock signal, to DRAM macros 14. The PLL 12 generates the internal clock signal by multiplying the frequency of the clock signal. The internal clock signal generated is distributed via buffer 13 to each macro cell in need of the internal clock signal. Part of the DRAM macros may be replaced by logic macro cells.
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