发明名称 |
HIERARCHICAL MEMORY ARCHITECTURE TO CONNECT MASS STORAGE DEVICES |
摘要 |
A hierarchical memory storage using a concentrator device that is located between a processor and memory storage devices to provide a succession of memory devices and enable attachment of a memory depth to a processor controller with a limited pin count.
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申请公布号 |
US2010250849(A1) |
申请公布日期 |
2010.09.30 |
申请号 |
US20090415991 |
申请日期 |
2009.03.31 |
申请人 |
EILERT SEAN |
发明人 |
EILERT SEAN |
分类号 |
G06F12/08;G06F11/08;G06F12/00;G06F13/14 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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