| 发明名称 |
A combined processing and non-volatile memory unit array |
| 摘要 |
A reconfigurable logic device comprises an array of tiles interconnected through a routing network, each tile comprises both a processing unit including volatile configuration memory and a Random Access Memory unit.
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| 申请公布号 |
EP2224344(A1) |
申请公布日期 |
2010.09.01 |
| 申请号 |
EP20090153966 |
申请日期 |
2009.02.27 |
| 申请人 |
PANASONIC CORPORATION |
发明人 |
STANSFIELD, ANTHONY;PRICE, NEIL |
| 分类号 |
G06F15/78;H03K19/177 |
主分类号 |
G06F15/78 |
| 代理机构 |
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