发明名称 CLOCK GENERATING CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a clock generating circuit which operates at high speed to generate an accurate clock signal for clock data recovery. <P>SOLUTION: A clock generating circuit includes a first voltage controlled oscillation circuit which outputs a first frequency signal in accordance with a first input voltage; a second voltage controlled oscillation circuit which outputs a second frequency signal in accordance with a second input voltage; a phase adjusting circuit which receives a control signal and controls the first input voltage and the second input voltage in such a way that a phase difference between the first frequency signal and the second frequency signal becomes a value corresponding to the control signal; a first determination circuit which detects and outputs a receiving signal synchronously to the first frequency signal; a second determination circuit which detects and outputs a receiving signal synchronously to the second frequency signal; and a phase detector which detects a phase of the receiving signal on the basis of the output of the first determination circuit and the output of the second determination circuit and controls the first input voltage and the second input voltage in accordance with a result of the phase detection. <P>COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010183452(A) 申请公布日期 2010.08.19
申请号 JP20090026560 申请日期 2009.02.06
申请人 FUJITSU LTD 发明人 TOMITA YASUMOTO;KIBUNE MASAYA;TAMURA YASUTAKA
分类号 H04L7/033;H03K5/26;H03L7/08 主分类号 H04L7/033
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