发明名称 SIGNAL GENERATION TIMING CONTROL PROGRAM AND INTEGRATED CIRCUIT PERFORMANCE TEST DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a signal generation timing control program for reducing simultaneous operation signals due to simultaneous transmission of electric signals by accurately arranging pins on a programmable device functionally separated from a large scale integrated circuit to reconfigure a reconfiguration integrated circuit. SOLUTION: The signal generation timing controlling program makes a computer function as, a timing shift calculation means S200 which calculates a shift width by which the output timing on output pin side is shifted, within the range of clock frequency of the large scale integrated circuit based on the accepted input/output pin information and a block inserting means S300 which inserts, in a reconfiguration integrated circuit, a clock shift block as the block for shifting the timing of signal transmission on the output pin side of the programmable device based on the shift width calculated by the timing shift calculation means S200, on the basis of input/output pin information which is accepted by a means S100 for accepting input/output pin information for each of programmable devices having been functionally separated from a large scale integrated circuit. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010177881(A) 申请公布日期 2010.08.12
申请号 JP20090016739 申请日期 2009.01.28
申请人 FUJITSU LTD 发明人 TOKUNAGA TAKAKAZU;SHIRAISHI HIROAKI;TAKATOMI KOJI;YOTSUMARU TAKEO
分类号 H03K19/173 主分类号 H03K19/173
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