发明名称 |
Integrated circuit modeling, design, and fabrication based on degradation mechanisms |
摘要 |
An integrated circuit (IC) includes at least a first complementary MOS (CMOS) circuit, the first CMOS circuit comprising one or more first n-channel MOS (NMOS) transistors and one or more first p-channel MOS (PMOS) transistors, where the first NMOS transistors and the first PMOS transistors are arranged in the first CMOS circuit to drive at least a first common node of the first CMOS circuit. An average of the effective gate channel lengths of the first NMOS transistors (first NMOS average length) is at least 2% greater than an average of the effective gate channel lengths of the first PMOS transistors (first PMOS average length).
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申请公布号 |
US7750400(B2) |
申请公布日期 |
2010.07.06 |
申请号 |
US20080192850 |
申请日期 |
2008.08.15 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
SHANWARE AJIT;KRISHNAN SRIKANTH |
分类号 |
H01L21/00 |
主分类号 |
H01L21/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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