发明名称 |
Fast transition from low-speed mode to high-speed mode in high-speed interfaces |
摘要 |
Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high-speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.
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申请公布号 |
US7752476(B2) |
申请公布日期 |
2010.07.06 |
申请号 |
US20070804413 |
申请日期 |
2007.05.17 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
MACRI JOSEPH;MOREIN STEVEN;LEE MING-JU E.;CHEN LIN |
分类号 |
G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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