EMBEDDED THROUGH SILICON STACK 3-D DIE IN A PACKAGE SUBSTRATE
摘要
An integrated circuit package has a die or die stack with through silicon vias embedded in a package substrate. A method of producing an integrated circuit package embeds at least one die with a through silicon via in a package substrate. The package substrate provides a protective cover for the die or die stack.
申请公布号
WO2010075331(A1)
申请公布日期
2010.07.01
申请号
WO2009US69102
申请日期
2009.12.22
申请人
QUALCOMM INCORPORATED;RAY, URMI;SWEENEY, FIFIN;KASKOUN, KENNETH;GU, SHIQUN;TOMS, THOMAS R.
发明人
RAY, URMI;SWEENEY, FIFIN;KASKOUN, KENNETH;GU, SHIQUN;TOMS, THOMAS R.