发明名称 OPTIMIZING QUIESCENCE IN A SOFTWARE TRANSACTIONAL MEMORY (STM) SYSTEM
摘要 A method and apparatus for optimizing quiescence in a transactional memory system is herein described. Non-ordering transactions, such as read-only transactions, transactions that do not access non-transactional data, and write-buffering hardware transactions, are identified. Quiescence in weak atomicity software transactional memory (STM) systems is optimized through selective application of quiescence. As a result, transactions may be decoupled from dependency on quiescing/waiting on previous non-ordering transaction to increase parallelization and reduce inefficiency based on serialization of transactions.
申请公布号 US2010162249(A1) 申请公布日期 2010.06.24
申请号 US20080344144 申请日期 2008.12.24
申请人 SHPEISMAN TATIANA;ADL-TABATABAI ALI-REZA;MENON VIJAY 发明人 SHPEISMAN TATIANA;ADL-TABATABAI ALI-REZA;MENON VIJAY
分类号 G06F9/46 主分类号 G06F9/46
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