| 发明名称 |
METHOD OF FORMING AN INTEGRATED POWER DEVICE AND STRUCTURE |
| 摘要 |
In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.
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| 申请公布号 |
US2010133610(A1) |
申请公布日期 |
2010.06.03 |
| 申请号 |
US20100696816 |
申请日期 |
2010.01.29 |
| 申请人 |
ROBB FRANCINE Y;ROBB STEPHEN P;VENKATRAMAN PRASAD;HOSSAIN ZIA |
发明人 |
ROBB FRANCINE Y.;ROBB STEPHEN P.;VENKATRAMAN PRASAD;HOSSAIN ZIA |
| 分类号 |
H01L27/088;H01L21/77;H01L29/78 |
主分类号 |
H01L27/088 |
| 代理机构 |
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