| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory access apparatus for enabling memory access processing at high speed. SOLUTION: The memory access apparatus 10 is provided with a processor 12, an I/F circuit 14, and a memory control circuit 16. The processor 12 is provided with an access-request generating circuit 12b which issues a memory access request. The I/F circuit 14 is provided with F/F circuits 24-30 which hold the memory access requests outputted from the processor 12 according to a clock signal. The memory control circuit 16 is provided with an access processing circuit 16a which executes access processing that complies with the memory access request held by the F/F circuits 24-30. The memory access request is held according to the clock signal, thereby shortening the delay of a transfer operation of the memory access request to the period of the clock signal. COPYRIGHT: (C)2010,JPO&INPIT |
