发明名称 PROCESSOR TO JTAG TEST ACCESS PORT INTERFACE
摘要 Method and apparatus for operating for operating an Institute of Electrical and Electronics Engineers (IEEE) Standard 1149.1 compliant Joint Test Action Group (JTAG) Test Access Port (TAP) controller are disclosed. An example apparatus includes write logic that is configured to operationally interface with a TAP controller and a processor. The write logic is further configured to receive, from the processor, data for initializing the apparatus and operating the TAP controller, convert at least a portion of the data from a parallel format to a serial format and communicate the converted data to the TAP controller.
申请公布号 US2010058130(A1) 申请公布日期 2010.03.04
申请号 US20080203109 申请日期 2008.09.02
申请人 SOMASUNDARAM SENTHIL;QIAN JUN 发明人 SOMASUNDARAM SENTHIL;QIAN JUN
分类号 G01R31/3177;G06F11/27 主分类号 G01R31/3177
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