发明名称 |
Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors |
摘要 |
A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a substantially equal and minimum size across the gate electrode level region. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication. Some of the conductive features extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the gate electrode level region is greater than or equal to eight.
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申请公布号 |
US2010032723(A1) |
申请公布日期 |
2010.02.11 |
申请号 |
US20090567609 |
申请日期 |
2009.09.25 |
申请人 |
TELA INNOVATIONS, INC. |
发明人 |
BECKER SCOTT T.;SMAYLING MICHAEL C. |
分类号 |
H01L27/088 |
主分类号 |
H01L27/088 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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