发明名称 RECEIVER ARCHITECTURE
摘要 A wireless receiver uses a joint detection Viterbi (JDV) algorithm to demodulate a signal that has a desired signal component and an interference signal component. The desired signal component includes a training sequence and at least one data field. The training sequence and a corresponding portion of the interference signal component is demodulated using the JDV algorithm to evaluate possible transmitted training sequences and interference signal sequences, and channel estimations for the desired signal component and the interference signal component are generated. The at least one data field is demodulated according to the JDV algorithm using the channel estimations as initial channel estimates for the JDV algorithm.
申请公布号 US2009304121(A1) 申请公布日期 2009.12.10
申请号 US20080198669 申请日期 2008.08.26
申请人 发明人 PEDERSEN CARSTEN AAGAARD;FATEMI-GHOMI NAVID;YAN AIGUO;TAYLOR JASON
分类号 H04L27/06 主分类号 H04L27/06
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