发明名称 DELAY LOCKED LOOP CIRCUIT AND DELAY LOCKING METHOD
摘要 A delay locked loop circuit includes a phase detecting unit for detecting a phase difference between a reference clock signal and a feedback clock signal, and for producing a phase difference detection signal, a code generating unit for producing a digital code signal according to the phase difference detection signal, a control current generating unit for generating a control current using the digital code signal, and a current controlled delay line for producing the feedback clock signal by delaying the reference clock signal by a delay time varied by the control current.
申请公布号 US2009278578(A1) 申请公布日期 2009.11.12
申请号 US20080332295 申请日期 2008.12.10
申请人 HYNIX SEMICONDUCTOR, INC. 发明人 KIM YONG-JU;HAN SUNG-WOO;SONG HEE-WOONG;OH IC-SU;KIM HYUNG-SOO;HWANG TAE-JIN;CHOI HAE-RANG;LEE JI-WANG;JANG JAE-MIN;PARK CHANG-KUN
分类号 H03L7/06 主分类号 H03L7/06
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