发明名称 Method and apparatus for reducing the processing rate of a chip-level equalization receiver
摘要 A method and apparatus for reducing the processing rate when performing chip-level equalization (CLE) in a code division multiple access (CDMA) receiver which includes an equalizer filter. Signals received by at least one antenna of the receiver are sampled at M times the chip rate. Each sample stream is split into M sample data streams at the chip rate. Multipath combining is preferably performed on each split sample data stream. The sample data streams are then combined into one combined sample data stream at the chip rate. The equalizer filter performs equalization on the combined sample stream at the chip rate. Filter coefficients are adjusted by adding a correction term to the filter coefficients utilized by the equalizer filter for a previous iteration.
申请公布号 US7573963(B2) 申请公布日期 2009.08.11
申请号 US20070824792 申请日期 2007.07.02
申请人 发明人
分类号 H04L1/02;H03H7/30 主分类号 H04L1/02
代理机构 代理人
主权项
地址