| 摘要 |
Phase jitter of the hybrid control type PLL circuit in a steady state is reduced. A steady state detection circuit determining whether an output of a phase comparison circuit in the hybrid control type PLL circuit frequently changes is provided, determination that a steady state has not been reached is made if the output of the phase comparison circuit does not change for a while, determination that the steady state has been reached if the output of the phase comparison circuit frequently changes, and based on a result of the determination, a control width of controlling a oscillation frequency of a voltage controlled oscillator circuit by a digital control signal is changed or (and) a frequency of changing an analog control signal is changed. Thereby, a control width of the oscillation frequency by the digital control signal after reaching the steady state can be reduced without damaging convergence before reaching the steady state. Therefore, the phase jitter in the steady state can be reduced.
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