| 摘要 |
A virtual zero delay unidirectional high voltage logic to low voltage CMOS logic voltage level translator can be achieved using a capacitive voltage divider coupled with the standard protection diodes commonly incorporated in low side logic (e.g. Xilinx Spartan-3E FPGA's). The complete voltage level translator will work equally well on frequencies from DC up to the rated operational frequency of the driver and receiver. Load side parasitic CMOS input capacitance in this case is ironically an asset rather than a liability since it can be used effectively as one element of the capacitive voltage divider. High voltage logic (e.g. 0 to 5V) can thus interface to lower voltage CMOS logic (e.g. 2.5V or 3.3V) with a minimum of additional external components and with virtually zero time delay.
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