| 摘要 |
Presently known d=1 codes have long trains consisting of consecutive 2T runs and an overall high frequency of occurrence of the shortest 2T runs that reduce the performance of the bit detector By using a code with an MTR constraint of 2 an improvement in the bit detection is achieved. A code constructed in a systematic way that provides an MTR constraint of 2 is presented. A variation of such a code is disclosed where one sub-code is used, where coding states are divided into coding classes and where code words are divided into code word types. Then, for a given sub-code, an code word of type t can be concatenated with an code word of the next sub-code if said subsequent code word of said next sub-code belongs to one of coding states of the coding class with index Tmax+1 t. In the code according to the invention the overall code has the property that the respective channel bit sequences that are encoded from the same message-bit sequence, starting from any possible state of the finite-state-machine, for each of the two values of a DC-control bit, that is part of a given user word have opposite parities for the sequences generated from the starting state up to the state where both encoder paths merge. For the case that the encoder paths do not merge, there is no such constraint. Finally, a new d=1, k=10 sliding-block decodable RLL code is disclosed with the following properties: (i) it has an r=2 constraint which is the lowest MTR value that is compatible with a rate R=2/3; (ii) it enables practical SISO-RLL decoding because of its compact 2-to-3 mapping; and (iii) the new code uses a parity-complementary word assignment4 (PCWA) for DC-control.
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