发明名称 METHOD OF ASSEMBLING A STACKED DIE SEMICONDUCTOR PACKAGE
摘要 <p>METHOD OF ASSEMBLING A STACKED DIE SEMICONDUCTOR PACKAGE A method of manufacturing a plurality of stacked die semiconductor packages, including: attaching a second silicon wafer to a first silicon wafer, wherein the second silicon wafer has a plurality of open vias; attaching a third silicon wafer to the second silicon wafer, wherein the third silicon wafer has a plurality of open vias, and the open vias of the second and third silicon wafers are aligned with one another; etching a bonding material that attaches the wafers from the aligned open vias; filling the aligned open vias with a conductor; forming conductive bumps at open ends of the aligned open vias; back grinding the first silicon wafer; separating the stacked semiconductor dies from each other; attaching the bump end of the stacked semiconductor dies onto a substrate; encapsulating the stacked semiconductor dies and substrate; and singulating the encapsulated assembly.</p>
申请公布号 SG148132(A1) 申请公布日期 2008.12.31
申请号 SG20080039455 申请日期 2008.05.22
申请人 UNITED TEST AND ASSEMBLY CENTER LTD. 发明人 KOLAN RAVI KANTH;SUN YI-SHENG, ANTHONY;HAO LIU;HOCK TOH CHIN
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