发明名称 INTEGRATED CIRCUIT DEVICE
摘要 <p>PURPOSE:To reduce the excessive power consumption to the least, in the LSI, by constituting the unit that the clock signal is not operated unless the key trailing signal is incoming even if the key is kept depressed, after the end of operation process. CONSTITUTION:In the clock control section CC, the system clock signal (outputs phi1 to phi3 of NOR gates OG1 to OG3) is produced together with the start of key depression and release of key depression, and the system clock signal is stopped with the halt instruction of the system clock signal caused from ROM at the end of operation (B)(in micro order). Accordingly, the control signal S supplies the system clock signal to the operation control means with the trailing signal of the key input (where: fk is the leading and trailing signal of key input) and the instruction (B) stops the supply to the operation control means (clock halt period), allowing to avoid the operation of the system clock signal unless the trailing signal is incoming with the key input, even if the key is remained depressed.</p>
申请公布号 JPS54144152(A) 申请公布日期 1979.11.10
申请号 JP19780053139 申请日期 1978.04.28
申请人 SHARP KK 发明人 HASHIMOTO SHINTAROU;NISHIMURA TOSHIO
分类号 G06F15/02;G06F1/04;G06F1/32 主分类号 G06F15/02
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