| 摘要 |
PURPOSE:To expand a range in which vector processing is capable by regulating the order rule between vector elements for the process accessing a main storage device. CONSTITUTION:When a processor is started, a control circuit 2 outputs a vector instruction reading request to the main storage device 1 through a bus 10. The read-out vector instruction is decoded by the control part 2 to check the status of a resource and a register necessary for the execution of the instruction. If these states satisfy the execution of the instruction, various information necessary for the execution of the instruction is read out from a ROM in the control circuit 2 and transmitted to the resource and register. When both the resource and register to be used can be used, the instruction is transmitted from a logical circuit 22 to a vector instruction starting information forming circuit 27. Simultaneously, the fetching of the succeeding vector instruction from the main storage device 1 is specified. |
