发明名称 INFORMATION PROCESSOR
摘要 PURPOSE:To reduce the delay caused by read-out of an indirect word and to realize reduction of the hardware quantity by producing a memory access address by means of the output of a data part which is obtained by retrieving an associative memory in response to the decoding of an instruction for execution of the indirect address qualification. CONSTITUTION:An indirect word is read out with execution of an indirect address qualifying instruction and an instruction word is set at an instruction register 101 of an advance control device 1. Thus an instruction is decoded and the contents of the register are read out. Then it is decided from said decoding action that the instruction word set at the register 101 is equal to an indirect address qualifying instruction. The signals showing that the address generating information on said instruction word are detected by the register detecting parts 112 and 113. Thus the indirect word detected by an indirect selecting part 114 is selected by an instruction register input selecting part 115 and set at the register 101. Based on this set indirect word, an operand address is produced and the operand data is read out. In such a way, the hardware quantity is reduced.
申请公布号 JPS63145533(A) 申请公布日期 1988.06.17
申请号 JP19860293228 申请日期 1986.12.09
申请人 NEC CORP 发明人 SAKAI NORIAKI
分类号 G06F12/10;G06F9/38;G06F12/08 主分类号 G06F12/10
代理机构 代理人
主权项
地址