发明名称 MULTIBITS RESISTANCE CHANGING MEMORY CELL ARCHITECTURE AND ITS WRITING METHOD
摘要 <p>A resistance changing memory unit cell includes a current control component operably coupled to a bit sense line, and a resistance changing memory element coupled between the current control component and a word line, wherein the current control component comprises a control terminal receiving a plurality of control signals and providing a current limiting function to at least three differing current levels.</p>
申请公布号 WO2008082852(A1) 申请公布日期 2008.07.10
申请号 WO2007US86780 申请日期 2007.12.07
申请人 SPANSION LLC;MASAO, TAGUCHI 发明人 MASAO, TAGUCHI
分类号 G11C13/00;G11C11/56 主分类号 G11C13/00
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