| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce design modifications to SDRAM controllers of existing processor chips designed for direct connection to dedicated SDRAMs when sharing an SDRAM and also SiP-packaging the existing processor chips. <P>SOLUTION: A translation module 104A disposed between a main processor chip 10 and a sub processor chip 11 in an information processing device 1 is connected to an SDRAM controller 113 of the sub processor chip 11 via all or part of the same signal line group that connects the SDRAM controller 113 to a dedicated SDRAM, to thereby interface the SDRAM controller 113 with a shared SDRAM controller 102 so that a sub CPU core 110 can access a shared SDRAM 3. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
