发明名称 Digital architecture for DFT/IDFT hardware
摘要 Embodiments of the present invention can provide circuits and systems for computing a discrete Fourier transform (DFT) or an inverse discrete Fourier transform (IDFT). An embodiment includes an input circuit, an intermediate circuit, an output circuit, and an accumulator circuit. The input circuit can receive a set of input values, and can use a first set of degenerate rotators to generate a first set of intermediate values. The intermediate circuit can receive the first set of intermediate values, and can use a set of CORDICs (coordinate rotation digital computers) to generate a second set of intermediate values. The output circuit can receive the second set of intermediate values, and can use a second set of degenerate rotators to generate a third set of intermediate values. The accumulator circuit can receive the third set of intermediate values, and can use a set of accumulators to generate a set of output values.
申请公布号 US2008281894(A1) 申请公布日期 2008.11.13
申请号 US20070801903 申请日期 2007.05.11
申请人 RAY BAIJAYANTA;KRISHNAN VENKATARAGHAVAN PUNNAPAKKAM;BALASUBRAMANIAN SRIRAM;SEETHARAMAN DALAVAIPATNAM RANGARAO 发明人 RAY BAIJAYANTA;KRISHNAN VENKATARAGHAVAN PUNNAPAKKAM;BALASUBRAMANIAN SRIRAM;SEETHARAMAN DALAVAIPATNAM RANGARAO
分类号 G06F15/00 主分类号 G06F15/00
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