| 摘要 |
In a hardware definition language (HDL) file among one or more files, one or more design entities containing a functional portion of a digital system are specified. The one or more design entities logically contain a plurality of latches having a respective plurality of different possible latch values that each corresponds to a different configuration of the functional portion of the digital system. With one or more statements in the one or more files, a multi-level Dial tree is defined that includes a selective control Dial (SCDial) entity at an upper level that is associated with at least one design entity. The SCDial entity has a Dial input, a plurality of Dial outputs coupled to inputs of the plurality of lower level Dials, and a mapping table indicating a mapping between each of a plurality of possible input values of the Dial input and a respective one of a plurality of sets of output values for the plurality of Dial outputs. At least one set of output values in the mapping table specifies output values for fewer than all of the plurality of Dial outputs. Each specified output value reflects a setting of at least one lower level Dial, and settings of the lower level Dials reflect which of the plurality of different possible configuration values is loaded in the plurality of configuration latches.
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