| 摘要 |
An improved technique that considerably reduces required logic and computational time for determining whether the difference between two multi-bit vectors is equal to a given number or lies between given two numbers in a digital logic circuit. In one example embodiment, this is accomplished by receiving a first N-bit vector A [N-1 :0] and a second N-bit vectorB [N- 1:0] in the digital logic circuit, where N is a non-zero positive number. A third N-bit vector is then obtained by performing a bit-wise AND (A [N-L0] & ~B[N-J: 0]) operation using A[N-L0] and ~ |
