发明名称 Method of testing apparatus having master logic unit and slave logic unit
摘要 An apparatus which is tested includes a master logic unit and a slave logic unit. The testing method includes accessing a virtual slave logic unit by a test pattern which includes an address for accessing and an expected value of a waiting time, returning a response value from the virtual slave logic unit which is accessed by the address after lapse of the waiting time, and comparing the expected value and the response value.
申请公布号 US7363565(B2) 申请公布日期 2008.04.22
申请号 US20050055629 申请日期 2005.02.11
申请人 OKI ELECTRIC INDUSTRY CO., LTD. 发明人 MURANISHI KOJI
分类号 G01R31/28;G06F11/22;G06F11/00;G06F13/00;G11C29/00 主分类号 G01R31/28
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