DELAY AMOUNT VARIABLE SHIFT REGISTER

摘要

PURPOSE:To miniaturize the circuit structure by using the 1st selection means which connects a selected terminal and the n-th shift register in series and the 2nd selection means which selects the delay amount of an optional bit within a range of delay amount of a prescribed bit of the n-th shift register and extracts the selected delay amount to a signal output terminal. CONSTITUTION:This device is provided with shift registers 1-n connected in series to a signal input terminal IN, a selection circuit Sa which selects a shift register connected in series to the register (n) and a selection circuit Sb which selects the delay amount of an optional bit of a shift register n0. In this case, shift registers 1-n and n0 have a delay amount of 8-bits respectively. The terminals (a)-(i) connected to the register n0 extract the delay amount of a 1-bit step; while terminals S1-Sn in the circuit Sa extract the delay amount of an 8- bit step respectively.