| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a PLL circuit with a small scale capable of correcting a phase offset. <P>SOLUTION: The PLL circuit comprises: a phase comparison circuit 10 for outputting an up-signal and a down-signal based on the phase difference between reference and feedback clock signals; an offset correction circuit 11 for correcting pulse widths of the up-signal and the down-signal to output a corrected up-signal and a corrected down-signal; a first charge pump circuit 12 for increasing or decreasing an output voltage based on the corrected up-signal and the corrected down-signal; and a voltage controlled oscillation circuit 14 for outputting an output clock signal where an oscillation frequency is controlled according to the voltage value of the output voltage. The offset correction circuit 11 sets at least one pulse width of either of the corrected up-signal and the corrected down-signal so that a charge pump output voltage reaches a nearly fixed value when the phase of the reference clock signal is aligned to that of the feedback clock signal. <P>COPYRIGHT: (C)2008,JPO&INPIT |
