| 摘要 |
An improved CMOS high-voltage latch stores data bits to be written to memory cells of a non-volatile memory has two cross-coupled CMOS inverters. One of the inverters has a pull-down leg that includes a pass-gate high-voltage NMOS transistor that is connected between a latch output node and a second high-voltage, low-threshold NMOS pull-down transistor that is connected to ground. A gate of the pass-gate high-voltage NMOS transistor receives a standby signal with a logic HIGH value of at most Vdd to turn on the pass-gate high-voltage NMOS transistor when the high-voltage CMOS latch is in a voltage mode of operation and during a high-voltage write mode of operation. The pass-gate high-voltage NMOS transistor thereby limits the voltage across the second high-voltage, low-threshold NMOS pull-down transistor to less than the standby signal in order to reduce punch-trough current and drain-to-substrate leakage of the second high-voltage, low-threshold NMOS pull-down transistor.
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