| 摘要 |
A memory device using a nanotube cell comprises a plurality of nanotube sub-cell arrays each having a hierarchical bit line structure including a main bit line and a sub-bit line. In the memory device, a nanotube cell array comprising a capacitor and a PNPN nanotube switch which does not require an additional gate control signal is located between a word line and the sub-bit line, so that a cross point cell array is embodied to reduce the whole chip size.
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